Last modified: 28 Jun 2018 10:27
This course addresses the design of digital electronic systems using synthesis techniques. The course commences with a discussion of design principles applicable to digital systems, including specification. Combinational logic, including minimisation, is studied. The course then turns to the use of VHDL for the simulation and synthesis of digital systems. The design of combinational logic, including arithmetic, and then synchronous sequential systems is considered. Coverage is sufficient to enable students to design simple combinational and sequential circuits and to use a synthesis tool.
|Session||Second Sub Session||Credit Points||15 credits (7.5 ECTS credits)|
The course initially overviews Boolean algebra and the optimisation of Boolean expressions. This includes an introduction to technology mapping. The VHDL hardware description language is then introduced as a means of describing standard digital components such as logic gates and multiplexors. Simulation and synthesis is discussed leading to the IEEE standard 1164. Synthesis of arithmetic circuits using IEEE numeric_std is described. The description of sequential logic via standard circuits such as latches and flip-flops is discussed for both simulation and synthesis. Finite state machines are then introduced with both manual and VHDL based design being considered. Both Moore and Mealy machines are discussed showing the advantages of each.
Complementary CMOS gates are described and the synthesis of circuits for such gates. This is followed by a discussion of power costs, power simulation, and a range of power saving techniques including clock gating and bus encoding.
Weekly CAD sessions are based on the use of Altera Quartus tools with demonstration boards using Altera FPGAs. Simulation is available via both ModelSim and Cadence’s NC tools. These weekly CAD sessions introduce students to the use of commercial design software and permit designs to be rapidly built on demonstration boards. The practical side of the course culminates in an 18 hour design exercise where students build an interface from an incremental shaft encoder using an FPGA, with the design synthesised from VHDL.
Information on contact teaching time is available from the course guide.
1st Attempt: 1 three-hour written examination paper (80%) and in-course assessment (20%).
There are no assessments for this course.
Feedback is provided for the elements constituting the continuous assessment.