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EG3560: DIGITAL ELECTRONIC SYSTEMS (2014-2015)

Last modified: 26 Jun 2014 14:37


Course Overview

This course addresses the design of digital electronic systems using synthesis techniques.  The course commences with a discussion of design principles applicable to digital systems, including specification. Combinational logic, including minimisation, is studied. The course then turns to the use of VHDL for the simulation and synthesis of digital systems.  The design of combinational logic, including arithmetic, and then synchronous sequential systems is considered. Coverage is sufficient to enable students to design simple combinational and sequential circuits and to use a synthesis tool. 

Course Details

Study Type Undergraduate Level 3
Session Second Sub Session Credit Points 15 credits (7.5 ECTS credits)
Campus None. Sustained Study No
Co-ordinators
  • Dr David Hendry

What courses & programmes must have been taken before this course?

  • One of EE2504 Electronic Systems (Passed) or EG2060 Electronics and Programmable Systems (Passed) or EG2503 Electrical and Mechanical Systems (Passed) or EG2504 Electronic Systems (Passed) or EG2559 Electrical and Mechanical Systems (Passed)
  • One of Engineering (EG) (Studied) or Bachelor of Engineering (Studied) or Master of Engineering (Studied) or Non-Graduating Student in Engineering Erasmus (Studied) or Non-Graduating Student in Engineering Iss (Studied) or Bachelor of Engineering in Engineering (Civil) (Studied) or Bachelor of Engineering in Eng (Civil with European Studies) (Studied) or Bachelor of Engineering in Eng (Civil with Management) (Studied) or Master of Engineering in Civil Engineering (Studied) or Bachelor of Engineering in Eng (Civil and Structural) (Studied) or Master of Engineering in Civil and Structural Engineering (Studied) or Master of Engineering in Civil & Structural Eng w Europ Std (Studied) or Bachelor of Engineering in Eng (Civil and Environmental) (Studied) or Master of Engineering in Civil and Environmental Engineering (Studied) or Master of Engineering in Civil & Environmental E w Europ Std (Studied) or Bachelor of Engineering in Engineering (Mechanical) (Studied) or Bachelor of Engineering in Eng (Mech with European Studies) (Studied) or Bachelor of Engineering in Eng (Mechanical with Management) (Studied) or Master of Engineering in Mechanical Engineering (Studied) or Master of Engineering in Mech Eng with Euro Studs (Studied) or Bachelor of Engineering in Eng (Mech with Oil & Gas Studies) (Studied) or Master of Engineering in Mechanical Eng w Materials (Studied) or Bachelor of Engineering in Eng (Electrical and Electronic) (Studied) or Bachelor of Engineering in Eng (Elec & Elec with Eur Stud) (Studied) or Master of Engineering in Electrical & Electronic Engineering (Studied) or Master of Engineering in Electrical & Electronic w Eur Stud (Studied) or Bachelor of Engineering in Eng (Electr'cs w Communications) (Studied) or Master of Engineering in Electronic Eng'g wth Communications (Studied) or Bachelor of Engineering in Eng (Electr'ncs w Comp Soft Eng) (Studied) or Master of Engineering in Electronic & Computer Engineering (Studied) or Master of Engineering in Civil Engineering with Management (Studied) or Master of Engineering in Mechanical Eng with Management (Studied) or Master of Engineering in Electrical & Electronic Eng w Man't (Studied) or Master of Engineering in Chemical Engineering (Studied) or Bachelor of Engineering in Chemical Engineering (Studied) or Master of Engineering in Petroleum Engineering (Studied) or Bachelor of Engineering in Petroleum Engineering (Studied) or Bachelor of Engineering in Eng (Mechanical and Electrical) (Studied) or Master of Engineering in Mechanical & Electrical Eng (Studied)
  • Any Undergraduate Programme (Studied)

What other courses must be taken with this course?

None.

What courses cannot be taken with this course?

Are there a limited number of places available?

No

Course Description

The course initially overviews Boolean algebra and the optimisation of Boolean expressions.  This includes an introduction to technology mapping.  The VHDL hardware description language is then introduced as a means of describing standard digital components such as logic gates and multiplexors.  Simulation and synthesis is discussed leading to the IEEE standard 1164.  Synthesis of arithmetic circuits using IEEE numeric_std is described. The description of sequential logic via standard circuits such as latches and flip-flops is discussed for both simulation and synthesis.  Finite state machines are then introduced with both manual and VHDL based design being considered.  Both Moore and Mealy machines are discussed showing the advantages of each. 

 

Complementary CMOS gates are described and the synthesis of circuits for such gates.  This is followed by a discussion of power costs, power simulation, and a range of power saving techniques including clock gating and bus encoding.

 

Weekly CAD sessions are based on the use of Altera Quartus tools with demonstration boards using Altera FPGAs.  Simulation is available via both ModelSim and Cadence‚Äôs NC tools.  These weekly CAD sessions introduce students to the use of commercial design software and permit designs to be rapidly built on demonstration boards.  The practical side of the course culminates in an 18 hour design exercise where students build an interface from an incremental shaft encoder using an FPGA, with the design synthesised from VHDL.

Further Information & Notes

Available only to students following an Honours degree programme.

Degree Programmes for which this Course is Prescribed

  • Bachelor of Engineering in Eng (Elec & Elec with Eur Stud)
  • Bachelor of Engineering in Eng (Electrical and Electronic)
  • Master of Engineering in Electrical & Electronic Eng w Man't
  • Master of Engineering in Electrical & Electronic Engineering
  • Master of Engineering in Electronic & Computer Engineering
  • Master of Engineering in Electronic Eng'g wth Communications

Contact Teaching Time

Sorry, we don't have that information available.

Teaching Breakdown

  • 0
    • None.
  • 1
    • None.
  • 2
    • None.

More Information about Week Numbers


Assessment

1st Attempt: 1 three-hour written examination paper (80%) and in-course assessment (20%).

Formative Assessment

None.

Feedback

Feedback is provided for the elements constituting the continuous assessment. 

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